The present invention generally relates to semiconductor devices, more particularly to packaging of semiconductor devices, and more particularly to an inverted J-lead package for power devices.
Power semiconductor packages have evolved from through hole to surface mounted packages with the evolution of printed circuit board technology. Surface mounted packages generally include a lead frame on which a semiconductor device is mounted. The semiconductor device and a portion of the lead frame are generally encapsulated with a resin material. In a leaded package, lead terminals extend outside the resin body and include bonding pads for providing a wire bond connection from the semiconductor device to the lead terminal.
Major considerations in the packaging of semiconductor devices include high thermal dissipation, low parasitic inductance, low electrical resistance between the semiconductor device and the circuit environment, good reliability in terms of thermal cycling and thermal shock/fatigue, and minimal consumption of circuit board space.
By way of illustration and with reference to FIG. 1, a conventional semiconductor package generally designated 1 includes a lead frame generally designated 7 having a lead frame pad 10 to which is coupled a die 8. A portion of the lead frame 7 may be molded in a resin body 2. In this embodiment, the die 8 embodies a MOSFET device and the lead frame 7 includes a source terminal 18, a gate terminal 26, and a drain terminal 11. Source terminal 18 of the lead frame 7 includes a plurality of separate source lead frame leads 18a external to the resin body 2 and a plurality of separate internal source bonding areas 16 where bonding wires 6 are bonded. Drain terminal 11 includes a plurality of separate drain lead frame leads 11a which are connected to the lead frame pad 10. The gate terminal 26 is connected to an internal gate bonding area 20 which in turn is connected to a gate pad 17 by means of wire 28.
FIG. 2 illustrates a top view of another conventional semiconductor package generally designated 4 including a lead frame generally designated 9. In this embodiment, in lieu of a plurality of separate source bonding areas 16 as shown in FIG. 1, the source bonding areas 16 are joined to form a single source bonding area 30 for bonding wires 6 to die 8. As with the embodiment of FIG. 1, the separate source lead frame leads 18a and the separate lead frame drain leads 11a are separate narrow metal strips that radiate externally from the resin body 2 and are adapted to be inserted into the same receptacle location on a printed circuit board as the device shown in FIG. 1.
Similar to the embodiment of FIG. 1, the lead frame 9 has die 8 disposed thereon and provides a generally narrow border frame around the perimeter of die 8. Moreover, the bonding area 20 of gate terminal 26 is coupled via wire 28 to gate pad 17 formed at a nearest corner. In the prior art embodiments, the source and gate bonding areas 16, 30 and 27 respectively share the same left side of the die 8. Likewise, the source leads 18a and the gate lead 26 radiate from the same left side.
Referring now to FIG. 3, a top view of a conventional dual-die semiconductor package generally designated 7 having a lead frame generally designated 13 is shown. The dual-die semiconductor package 7 includes a pair of dies 50a and 50b mounted on a lead frame pad 52 and molded in a resin body 2. A first source terminal 18a includes a first source terminal bonding area 16a distributed along a left side of the first die 50a. The first source terminal bonding area 16a is connected to the first die 50a via bonding wires 6a. A first gate terminal 26a includes a first gate bonding area 20a that shares the left side of the first die 50a and is connected to the first die 50a via bonding wire 28a. A plurality of first drain terminals 11a are coupled to lead frame pad 52.
A second source terminal 18b includes a second source terminal bonding area 16b distributed along a left side of the second die 50b. The second source terminal bonding area 16b is connected to the second die 50b via bonding wires 6b. A second gate terminal 26b includes a second gate bonding area 20b that shares the left side of the second die 50b and is connected to the second die 50b via bonding wire 28b. A plurality of second drain terminals 11b are coupled to lead frame pad 52.
With reference to FIG. 4, a cross sectional view of a conventional semiconductor package such as semiconductor package 1 is shown. Die 8 is shown having a top surface 22 to which bonding wire 6 is coupled. Die 8 may be coupled to lead frame pad 10 by means of conventional material 12. Leads 18 and 11 are shown formed in a conventional “J” configuration. This configuration suffers the disadvantage of requiring that a portion of a printed circuit footprint be utilized for the leads 18 and 11.
A prior art leaded package is disclosed in U.S. Pat. No. 6,291,262 entitled “Surface Mount TO-220 Package and Process for the Manufacture Thereof”. The disclosed package includes leads which are bent within the molded housing and formed prior to molding the housing around the lead frame. The bend is located inside the package body to minimize mechanical stresses on the package body. Although the portion of the lead extending outside the package is reduced, the leads still consume valuable footprint real estate.
Another prior art leaded package is disclosed in U.S. Pat. No. 6,211,462 entitled “Low Inductance Power Package for Integrated Circuits”. The package includes a flat lead frame with internal leads formed upward to be in very close proximity to the lead frame pad. The external leads are flat and extend beyond the package edge so that good solder connections to a printed circuit board can be made and inspected.
A prior art solution to the use of leaded packages includes leadless packages. One such leadless package is disclosed in U.S. Pat. No. 4,682,207 entitled “Semiconductor Device Including Leadless Packages and a Base Plate for Mounting the Leadless Packages”. Each leadless package includes a semiconductor chip housed therein and a plurality of electrodes formed on the four side surfaces and lower surface thereof. Leadless packages suffer the disadvantage of making the inspection of solder joints difficult.
As can be seen, there remains a need in the art for a semiconductor package that minimizes the consumption of circuit board space. Such a semiconductor package also preferably allows for easy inspection of solder joints while providing increased die size, reduced package height, and improved thermal resistance properties. Finally such a semiconductor package preferably provides for reduced on-resistance and inductance.